There are two major classes of cells, sometimes called application specific integrated circuits (ASIC), commonly used to allow designers to place large numbers of logic circuits on a single or common very large scale integrated (VLSI) chip. One of these classes or types of cells is known as a standard cell, wherein each logical function, which may be referred to as a book, is implemented as a custom designed circuit which can then be placed in a predefined area or cell boundary anywhere on the chip and be wired to other functions, circuits or books. In this standard cell approach, the sizes of the devices or transistors and the layout of the circuits are optimized for each logical function or book so that density and performance characteristics are nearly comparable to a custom designed chip. In the standard cell, most or all steps in the fabrication of the wafer or chip are personalized for each particular design. Thus, if any changes are to be made to the design, an entirely new mask must be made for every personalized step in the fabrication process and the fabrication must again begin from a bare semiconductor, e.g., silicon, wafer. Standard cells are discussed in some detail in an article entitled, "HAPPI: A Chip Compiler Based On Double-Level-Metal Technology" by R. Putatunda et al, 23rd Design Automation Conference, paper 41.4, pp. 736-743, 1986, and in an article entitled, "Philo, A VLSI Design System," by R. Donze, Design Automation Conference, Las Vegas, Nev., Jun. 1982, pp. 163-169.
In contrast to the standard cell, gate array cells are not personalized until the fabrication process reaches the first contact level to the conductive material which interconnects the devices or transistors in the gate array cell for a particular design. That is, a gate array chip is formed by making rows of transistors, P-channel and N-channel transistors if complementary metal oxide semiconductor (CMOS) technology is used, arranged in cells on the surface of the chip. For each discrete logic function available in the library of books for the chip, a personality of conductors is defined in a known manner which interconnects the devices or transistors located within one or more cells to perform a desired function, such as inverting or latching. Any logical function implemented on the gate array chip uses the same set of background devices or transistors and, if any changes are to be made in the circuit, only the last few steps, the conductor and contact steps, in the fabrication process need to be altered to rearrange the interconnections. By using the gate array cell approach, both initial designs and later modifications can be obtained more quickly and cheaply than in a standard cell design, though with some impact to chip performance and density when compared to that of the standard cell. Gate array cells are discussed in some detail in U.S. Pat. No. 4,412,237 by N. Matsumura et al, filed on Dec. 11, 1978 and issued on Oct. 25, 1983, and U.S. Pat. No. 4,589,007 by S. Kuboki et al, filed Sep. 6, 1983, and issued May 13, 1986, and in commonly assigned U.S. patent application No. having Ser. No. 814,122, filed on Dec. 27, 1985, by J. Blachere et al and entitled, "Multi-Functional Pre-diffused Arrays in CMOS Technology."
In a standard cell design, each book or functional circuit is laid out on the surface of the chip within one or more cells following boundary restrictions defining active circuit areas which allow it to be placed next to any other book or member of the library without interference between them. The boundary restrictions are determined by ground rules dependent upon the technology used to make the chip. In standard cell chips the region between active circuit areas is generally converted into an insulating region, such as a thick oxide, to provide isolation between books. In gate array cell design, each book is also laid out on the surface of the chip within one or more cells except that each book is essentially only an arrangement of interconnections to the transistors located within the one or more cells, but again each book must not interfere with a neighboring or adjacent book or circuit. Gate arrays typically use gate or electrical isolation techniques rather than oxide isolation to prevent adjacent books from interfering with each other. In the gate isolation technique, interconnections are included in each book to turn off the background transistors at one end of the book so as to electrically isolate adjacent diffusion nodes or regions. The gate isolation technique has been shown to provide improved density over that obtained by placing thick oxide isolation between adjacent diffusion nodes or regions, because the book designer is provided increased flexibility when connecting transistors for a particular circuit. Gate or electrical isolation is discussed in some detail in U.S. Pat. No. 4,562,453 by T. Noguchi et al, filed Nov. 8, 1982, and issued Dec. 31, 1985, and U.S. Pat. No. 4,570,176 by K. D. Kolwicz, filed Apr. 16, 1984, and issued Feb. 11, 1986.
In U.S. Pat. No. 4,513,307 by J. L. Brown, filed May 5, 1982, and issued Apr. 23, 1985, there is disclosed a CMOS gate array which uses two different cell layouts on the same chip to improve the utilization of background transistors. The gate array contains a continuing pattern of two sets of three series connected transistors in a cell surrounded by cells each containing two single transistor gates of each channel type.
An intermix of cells or circuits on a common chip to improve performance and to reduce the occupation area of semiconductor circuits is disclosed in Japan Patent 60-177650 dated Sep. 11, 1985. Other references disclosing an intermix of cells or circuits may be found in IEEE 1985 Custom Integrated Circuits Conference, pp. 252-257, "Structured Arrays--A New ASIC Concept Provides the Best Gate Arrays and Cell Based Custom" by R. Walker et al and in IEEE 1986 Custom Integrated Circuits Conference, pp. 565-567, "Configurable 6845 Megacell Incorporated With 2 UM CMOS Gate Array" by K. Pierce et al.
As can be appreciated, the design and fabrication of any of the dense logic chips referred to hereinabove requires very complex processes. To assist in these processes, a considerable number of process steps have been automated and controlled by computers. Some procedures and equipment used to assist in the fabrication of such logic chips is disclosed, e.g., in Proceedings of the IEEE International Conference on Computer Design, pp. 221-224, Oct. 7-10, 1985, "A Software Environment for Building Core--Microcomputer Compilers" by T. G. Matheson et al, and in Electronic Design, pp. 135-142, Dec. 12, 1985, "Programming Language Makes Silicon Compilation A Tailored Affair" by M. R. Burich.
In the logic design technology, it is desirable to provide standard cells with the highest possible circuit density and high utilization of chip surface area while providing a process or method which can rapidly modify sections of the chip as required without significantly altering the original standard cells.